RIO Developer Essentials Guide for Academia

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Guides, code examples, and procedures

Introduction to the "Developer Essentials Guide" and software setup

An overview of what this guide has to offer as well as software requirements and setup information.

NI RIO
RIO guide

Introduction to the NI RIO platform.

NI Academic RIO Device
RIO guide

Introduction to the NI Academic RIO Device platform.

Application examples
RIO guide

LabVIEW and Academic RIO work together to offer a comprehensive platform for all of your embedded control and monitoring requirements. These application examples highlight what you can accomplish and will be helpful to jumpstart your own project development.

"Embedded Control and Monitoring" video
RIO guide

This 3-minute video from NI introduces the basic ideas behind embedded control and monitoring (ECM) with the NI reconfigurable I/O (RIO) hardware and software platform which includes the Academic RIO Device products.

Software architecture for RIO embedded control and monitoring applications
RIO guide

A standard software architecture that lends itself to a wide variety of system controller designs that require a PC-based user interface.

NI Academic RIO Device architecture overview
RIO guide

A high-level overview of the Academic RIO Device architecture and features.

Academic RIO Device Toolkit Express VIs
RT guide

Develop Academic RIO Device applications by writing code exclusively for the RT target, and use Express VIs to access the wide variety of I/O devices implemented by the default Device FPGA personality.

Real-Time (RT) programming: Basic procedures
RT guide

Create a new LabVIEW project for the RT target, use the Academic RIO Device Toolkit and default FPGA personality, and deploy a VI as the start-up application.

Make your first RT application
RT procedure

Follow along with this step-by-step tutorial to make a "hello, world!"-like application to experience the advantages of multiple linked VIs running simultaneously on the real-time (RT) target and desktop computer: (1) "RT Main" runs as the RT target start-up VI, blinks the onboard LEDs, and reads the onboard button; these onboard devices physically connect to the FPGA I/O pins which are accessed with the Academic RIO Device Toolkit Express VIs and default FPGA personality, and (2) "PC Main" VI runs on the desktop computer as a user-friendly human-machine interface (HMI) for remote command and control of "RT Main" through the network via shared variables hosted on the RT target.

Create a new RT project
RT procedure

Set up a LabVIEW project for an RT VI.

Deploy a startup application
RT procedure

Deploy a LabVIEW VI as a 'startup application' that runs automatically immediately after the Academic RIO Device boots up.

RT programming: FPGA personalities
RT guide

The FPGA "personality" (bitstream configuration file) determines how the RT target interacts with peripheral devices. The personality can also implement custom functionality.

I/O Monitor
RT procedure

Interactively set output values and monitor input values on the Academic RIO Device MXP and MSP connector signals to quickly test your connected peripheral devices without creating a VI. Note: The NI ELVIS III does not have an I/O Monitor at this time.

Develop an FPGA VI
FPGA guide

Develop your own FPGA-targeted VI to take advantage of the unique capabilities of the FPGA target such as high-speed I/O, precision I/O timing, parallel processing, and functionality not offered by the RT processor and Academic RIO Device Toolkit default personality; you can also augment the default personality with your needed capability.

Make your first FPGA application
FPGA procedure

Follow along with this step-by-step tutorial to make a "hello, world!"-like application to experience the advantages of multiple linked VIs running simultaneously on the FPGA target, real-time (RT) target, and desktop computer: (1) "FPGA Main" VI blinks the onboard LEDs and reads the onboard button; these onboard devices physically connect to the FPGA I/O pins, (2) "FPGA testbench" VI runs on the desktop computer for interactive development and debugging of "FPGA Main" in simulation mode prior to compiling to a bitstream file, (3) "RT Main" VI runs as the RT target start-up VI; it runs "FPGA Main", interacts with its front-panel controls/indicators, and communicates with an external desktop computer via network-published shared variables, and (4) "PC Main" VI runs on the desktop computer as a user-friendly human-machine interface (HMI) for remote command and control of "FPGA Main" through the network.

Create a new FPGA project
FPGA procedure

Set up a LabVIEW project for a fully custom FPGA VI.

FPGA programming: Simulation techniques
FPGA guide PC guide

Run the VI with simulated I/O or create a testbench on the PC host to apply a test sequence as the FPGA VI input and monitor the resulting output sequence.

Simulate an FPGA VI
FPGA procedure

Debug your FPGA VI before compiling to a bitfile using execution highlighting, breakpoints, probes, and sampling probes.

"Desktop Execution" node as an FPGA VI testbench
FPGA code PC code

The PC VI interacts with the FPGA VI in simulation mode to apply a test sequence as the FPGA VI input and monitor the resulting output sequence.

Compile an FPGA VI
FPGA procedure

Compile your FPGA VI to a bitfile using your own computer or a cloud-based compiler.

Derived clock domains
FPGA code

Use a derived clock domain to effectively speed up or slow down the FPGA's 40-MHz clock for a selected portion of the FPGA block diagram.

FPGA programming: IP blocks
FPGA guide

Reuse (import) VHDL code and configure Xilinx IP blocks as drop-in components on the LabVIEW block diagram.

"IP Integration" node for VHDL code reuse
FPGA code

Reuse existing and validated VHDL-based circuit functionality in the FPGA block diagram instead of developing new LabVIEW G code to implement the same functionality.

Xilinx IP integration
FPGA code

Configure and use Xilinx IP (intellectual property) modules designed specifically for the Xilinx Zynq FPGA

Modify the default Academic RIO Device FPGA personality
FPGA procedure

Add your own functionality to the default Academic RIO Device FPGA "personality" (bitfile) to retain selected Device Express VI capabilities.

RT procedures: System administration
RT guide

Set the administrator password to secure your Academic RIO Device system, adjust the system time and date, and manage the installed software set add-ons.

Set the password for the system administrator ("admin") user
RT procedure

Secure your Academic RIO Device system from unauthorized access by setting the password for the "admin" user and removing all permissions from the "everyone" group.

Manage the Academic RIO Device software set add-ons
RT procedure

You will need to enable some software set add-ons to make some built-in LabVIEW VIs work properly on the RT target, for example, 'SMTP client with SSL support' (for secure email) and 'HTTP Client with SSL Support' (for secure HTTP).

Set RT system time and date from a browser
RT procedure

Browse directly to the Academic RIO Device network address to use the Web-Based Monitoring and Configuration tool. Note: The NI ELVIS III does not have the Web Interface for modifying these settings. Use NI Measurement and Automation Explorer (NI MAX) to modify these settings instead.

Set RT system time and date from NI MAX
RT procedure

Use the NI Measurement & Automation Explorer (NI MAX) application.

Set RT system time/date from PC
RT code PC code

Use the "Set Time" function to adjust the RT system time to match the (assumed accurate) PC system time. Restart the RT target to save the current RT time to be reloaded on each reboot of the Academic RIO Device.

Synchronize the system clock to a NIST time source
RT code

Synchronize the system clock time based on querying the Internet Time Service (ITS) maintained NIST (National Institute of Standards and Technology): Open a TCP/IP connection to the "Daytime Protocol" port 13, read the 51-character string, parse the string for time and date information, validate the result (look for a server health indicator and a "magic string"), and then adjust the system time.

RT procedures: File system
RT guide PC guide

Connect to the Academic RIO Device file system through your browser with "Web-Based Monitoring and Configuring" or by mounting the file system as a drive on your host PC with WebDAV.

Connect to the Academic RIO Device file system with a web browser
RT procedure PC procedure

View the Academic RIO Device file system through your web browser; files may be downloaded with this technique, too.

Connect to the Academic RIO Device file system with WebDAV
RT procedure PC procedure

Mount the Academic RIO Device file system as a network drive on your Windows, Mac OS, or Linux system, and then directly manipulate the files as you would any other files on your system.

Headless datalogger and file I/O
RT code

Monitor process variables and sensor measurements, timestamp them, and log them to a file, and then remote access the datalog file through the network with WebDAV, web browser, or VI running on a PC host.

RT programming: Timed loops
RT guide

A "timed loop" is a while-loop structure that executes at a precise user-specified rate. Timed loop are particularly useful for process control loops that demand a reliable update rate.

Timed loop
RT code

Use the "Timed Loop" to create a deterministic process loop, i.e., a loop that runs with a precisely-defined time per iteration.

Measure loop iteration time
RT code

Use the "Tick Count" function to measure the total elapsed time per iteration of a process loop.

RT programming: Interrupts
RT guide

Use an onboard timer or an external event interrupt request (IRQ) to immediately execute a task.

Externally-triggered action using interrupt request (IRQ)
RT code

Run a callback VI each time that a digital input transition or an analog input voltage threshold crossing generates an interrupt request (IRQ).

Timer-driven background process using interrupt request (IRQ)
RT code

Run a callback VI each time that an FPGA-based interval timer generates an interrupt request (IRQ).

RT inter-process communication
RT guide

Exchange data between process loops running in parallel on the RT target.

Local variable (RT)
RT code

Use a local variable (front-panel indicator) to communicate between two parallel process loops contained within the same VI, and use a local variable to stop parallel loops with one "stop" button.

Global variable (RT)
RT code

Use a global variable to communicate between two parallel process loops contained within different VIs under the same target, and use a global variable to stop parallel loops with one "stop" button.

Single-process shared variable (SPSV)
RT code

A single-process shared variable (SPSV) behaves like a global variable that links deterministic and non-deterministic process loops, effectively shielding the deterministic loop from elements that contribute jitter.

Functional global variable (FGV)
RT code

Use a functional global variable (FGV) to communicate between two parallel process loops contained within different VIs under the same target, and use a FGV to stop parallel loops with one "stop" button. The "functional" nature of the FGV means that you can create additional functionality beyond that of a basic global variable, e.g., counting and calculations that operate on the stored value.

Queue
RT code

Use a queue to send messages and data between two or more parallel process loops contained within a VI or other VIs. Queues also serve as the foundation for the "Queued State Machine" design pattern.

Channel wire
RT code

Use a channel wire to communicate between two (or more) parallel process loops contained within the same VI, and use a channel wire to stop parallel loops with one "stop" button. Requires LabVIEW 2016 or later version.

FPGA inter-process communication
RT guide

Exchange data between process loops running in parallel on the RT target.

Local variable (FPGA)
FPGA code

Use a local variable (front-panel indicator) to communicate between two parallel process loops contained within the same VI.

Global variable (FPGA)
FPGA code

Use a global variable to communicate between two parallel process loops contained within different VIs under the same target.

RT/host inter-target communication
RT guide PC guide

Transfer data, commands, and status between the RT target and a host system.

Programmatic front-panel communication with RT
FPGA code RT code

The RT VI operates (writes) the front-panel controls of the FPGA VI and reads its indicators.

RT procedures: Network-published shared variables (NPSVs)
RT guide PC guide

An NPSV behaves like a global variable to connect the RT target and PC host through a network.

Create a network-published shared variable (NPSV)
RT procedure PC procedure

The network-published shared variable (NPSV) behaves like a global variable to link targets through the network.

Bind a PC VI front-panel indicator to a network-published shared variable (NPSV)
RT procedure PC procedure

A quick and easy way for a PC HMI (human-machine interface) VI to observe the state of an RT-hosted network-published shared variable (NPSV) without creating any block diagram code; an alternative to programmatically accessing the NPSV value.

Network-published shared variable (NPSV)
RT code PC code

A network-published shared variable (NPSV) behaves like a global variable that links process loops residing in two or more network-connected targets.

Programmatically access a network-published shared variable (NPSV)
RT code PC code

Use the NPSV programmatic API (application programmer's interface) VIs as an alternative method to a shared variable node.

Send messages through a network stream channel
RT code PC code

Send command and status messages through a low-latency lossless network-based data communication channel between the RT target and PC host system.

Stream high-speed data through a network stream channel
RT code PC code

Efficiently transfer blocks of data between the RT and PC by network streams.

Stream high-speed data between FPGA and RT with a DMA FIFO
FPGA code RT code

Efficiently transfer blocks of data between the RT and FPGA by direct memory access (DMA) first-in first-out (FIFO) buffers.

Augmented default Academic RIO Device FPGA personality and high-precision waveform measurement application example
FPGA code RT code

Load and run a modified version of the default Academic RIO Device personality (FPGA bitfile) augmented by user-defined functionality, for example, to make a high-precision measurement of pulse width.

FPGA/RT and FPGA/host inter-target communication
FPGA guide RT guide PC guide

Transfer data, commands, and status between the FPGA target and a host system (RT or PC).

Programmatic front-panel communication with PC
FPGA code PC code

The PC VI operates (writes) the front-panel controls of the FPGA VI and reads its indicators.

Stream high-speed data between FPGA and PC with a DMA FIFO
FPGA code PC code

Efficiently transfer blocks of data between the PC and FPGA by direct memory access (DMA) first-in first-out (FIFO) buffers.

RT programming: Queue-based state machines
RT guide PC guide

Queue-based state machines excel at implementing system control, data measurement and processing, and other tasks to respond to inputs from the surrounding physical system and user interface. Learn about three popular design patterns: queued state machine (QSM), queued message handler (QMH), and event-driven producer-consumer loops.

Queued state machine
RT code

State machines perform system control, data processing, and any task that involves executing a sequence of activities in response to inputs from the surrounding physical system, the user interface, and other processes within the system. The queued state machine is a particular implementation style that is flexible and versatile, easy to maintain, and computationally efficient.

Queued message handler with multiple process loops
RT code

The queued message handler contains multiple process loops operating independently and in parallel that communicate with each other by sending messages through queues. Each process is a well-defined task implemented by the "Queued State Machine" design pattern. Breaking up the system into self-contained tasks greatly simplifies the design of complex systems.

System controller application example: Home Security System
RT code PC code

Example of a complete RT system controller based on the Queued Message Handler (QMH) design pattern with multiple parallel task loops implementing behaviors with queued state machines (QSMs), various inter-process communication techniques (queues and local variables), and inter-target communication techniques (network-published shared variables (NPSVs) and network streams). The PC host human-machine interface (HMI) can remotely connect to the system through the network, monitor the status of the security system, and control it remotely.

Event-driven producer-consumer state machine
PC code

Create a responsive user interface based on two loops operating in parallel: the "producer" loop event structure responds immediately to user interactions such as button clicks and mouse movements that send commands through a queue to the "consumer" loop which performs the required tasks. Separating the state machine into two loops allows the user interface to remain responsive should a consumer task require an unusual amount of time or must wait for a shared resource to become available.

RT networking: Get connected
RT guide

Set up wired and wireless networks and connect to the Internet.

Connect to a home wireless router
RT procedure

Connect an Academic RIO Device to a home wireless router to gain access to the Internet. Note: The NI ELVIS III does not have the Web Interface for modifying these settings. Use NI Measurement and Automation Explorer (NI MAX) to modify these settings instead.

Create a wireless ad-hoc network with two or more Academic RIO Devices
RT procedure

Set up one Academic RIO Device to serve as the ad-hoc network host, and then set up additional Devices to join the ad-hoc network. Note: The NI ELVIS III does not have the Web Interface for modifying these settings. Use NI Measurement and Automation Explorer (NI MAX) to modify these settings instead.

Create an Internet-capable wired network with PC
RT procedure PC procedure

Connect the Academic RIO Device to a PC with a wired network (Ethernet) and establish the Device's Internet connection by sharing the PC wireless connection to a home wireless router. Note: The NI ELVIS III does not have the Web Interface for modifying these settings. Use NI Measurement and Automation Explorer (NI MAX) to modify these settings instead.

RT networking: IP addresses
RT guide PC guide

Display available IP addresses on the PC host and RT target; learn my public Internet IP address by calling a Web service.

Determine the network address of an Academic RIO Device
RT procedure

Use NI MAX to learn the network address (IP address) of your Academic RIO Device.

Show available IP addresses
RT code PC code

Display all of the network IP (Internet Protocol) addresses at which the RT target or PC host can be reached.

RT networking: email
RT guide

Send email (including attached files) and text messages from the Academic RIO Device.

Send an email or text message
RT code

Use the Simple Mail Transport Protocol (SMTP) to send an email message; send the email to an SMS (Short Message Service) gateway service to forward the email as a text message.

Send a file as an email attachment with high priority (remote webcam photo logger application)
RT code

Use the low-level Simple Mail Transport Protocol (SMTP) VIs create an email, attach a file, and set the email header to flag the message as 'high priority' in the recipient's email application. The illustrative application example captures webcam images at regular intervals and sends them as email attachments.

RT networking: Transmission Control Protocol (TCP)
RT guide

TCP is a reliable connection-based IP networking protocol used between LabVIEW applications as well as other IoT devices.

Check Internet access (HTTP method)
RT code PC code

Determine whether or not Internet access is available by attempting an HTTP connection to the "Microsoft Network Connectivity Status Indicator" (NCSI) web service.

Check Internet access (TCP method)
RT code PC code

Determine whether or not Internet access is available by attempting a TCP connection to the "Microsoft Network Connectivity Status Indicator" (NCSI) web service.

TCP/IP sender and receiver and "TCP ping" application
RT code PC code

Send TCP/IP messages to a destination IP address and port number, listen for incoming TCP/IP messages on a user-defined port, and echo received messages back to the source. Combine the sender and receiver into a single "TCP ping" application to test the communication channel between two network hosts, and illustrate the notifier method to stop parallel loops with one "stop" button.

TCP client-server
RT code PC code

Create a server on the Academic RIO Device that listens for TCP/IP network connection requests from a client running on the PC host, accepts client information including the desired state of the four onboard LEDs, sets the LEDs accordingly, and returns the state of the onboard 3-axis accelerometer and pushbutton.

RT networking: User Datagram Protocol (UDP)
RT guide

UDP is a simple and efficient connectionless IP networking protocol used between LabVIEW applications as well as other IoT devices.

UDP sender and receiver and "UDP ping" application
RT code PC code

Send UDP messages to a destination IP address and port number, listen for incoming UDP messages on a user-defined port, and echo received messages back to the source. Combine the sender and receiver into a single "UDP ping" application to test the communication channel between two network hosts, and illustrate the notifier method to stop parallel loops with one "stop" button.

UDP client-server
RT code PC code

Create a server on the Academic RIO Device that listens for UDP datagram messages from a client running on the PC host, accepts client information including the desired state of the four onboard LEDs, sets the LEDs accordingly, and returns the state of the onboard 3-axis accelerometer and pushbutton.

RT networking: Web services
RT guide

Use the infrastructure of the Web for machine-to-machine exchange of information.

Web services overview
RT guide

A "Web service" uses the infrastructure of the Web for machine-to-machine exchange of specific information. The Academic RIO Device can call Web services to retrieve information and can also host Web services to provide information to other systems.

Web services: calling a Web service technical principles
RT guide

Learn the technical principles necessary to create VIs that can call Web services which return information in the form of JSON strings.

Call a Web service
RT code

Form a query string as a URL, retrieve the JSON string served by the Web service, and parse the JSON string to extract useful information.

Web services: hosting a Web service technical principles
RT guide

Learn the technical principles necessary to host a Web service on the Academic RIO Device. Remote clients such as another LabVIEW-based target, an IoT device, or a conventional browser can retrieve sensor measurements and control indicators and actuators using commands obtained from the remote client's request query string.

Host a Web service
RT code

Host a web service on the Academic RIO Device to serve the states of onboard sensors (pushbutton and accelerometer) and system information (date, time, host name, and IP address), and to control the onboard LEDs based on a user-selected LED hex code.

LabVIW block diagram elements:

Binary Counter
Boolean Crossing
Build Path
Callback VI Reference
Clear Errors
Close
Close FPGA VI Reference
Close File
Close Handle
Close Variable Connection
Create Network Stream Reader Endpoint
Create Network Stream Writer Endpoint
Create Timer Interrupt
Date-Time To Seconds
Dequeue Element
Desktop Execution node
Destroy Stream Endpoint
Destroy Timer Interrupt
Enqueue Element
Enqueue Element at Opposite End
Error Ring
Event Structure
FIFO Method Node
Feedback Node
First Call?
Flat Sequence Structure
Flatten To JSON
Flush Stream
Format Date-Time String
Format Into File
Format Into String
Get Date-Time In Seconds
Get Date-Time String
Get Notifier Status
Get Number of Records
Get Queue Status
Get Time-Date String
Global Variable
HTTP Get
IP Integration node
IP To String
Initialize Session
Interrupt
Invoke Method
Invoke Node
Join Numbers
Local Variable
Loop Timer
Obtain Notifier
Obtain Queue
Open FPGA VI Reference
Open Handle
Open Variable Connection
Open-Create-Replace Datalog
Property Node
Read Datalog
Read Form Data
Read Multiple Elements from Stream
Read Postdata
Read Single Element from Stream
Read Variable
Read-Write Control
Recursive File List
Register Analog Input Interrupt
Register Digital Input Interrupt
Release Notifier
Release Queue
Restart
Scan From File
Scan From String
Send
Send Email
Send Notification
Set Attachments
Set Custom Bitfile
Set Datalog Position
Set HTTP Response MIME Type
Set Headers
Set Message
Set Recipients
Set Time
Single-Cycle Timed Loop
Split Number
String To IP
TCP Close Connection
TCP Create Listener
TCP Open Connection
TCP Read
TCP Wait On Listener
TCP Write
Tick Count (ms)
Timed Loop
UDP Close
UDP Open
UDP Read
UDP Write
Unflatten From JSON
Unregister Interrupt
Vision Acquisition
Wait Until Next ms Multiple
Write Datalog
Write Multiple Elements to Stream
Write Response
Write Single Element to Stream
Write Variable

Targets:

FPGA
PC
RIO
RT

Communications:

FPGA-PC
FPGA-RT
Inter-process
Inter-target
Latest value
Message
NPSV
PC-FPGA
Queue
RT-FPGA
RT-PC
Streaming
Tag

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