Home
Quickstart Guide
Introduction RIO Academic RIO Application examples Your first RT app Your first FPGA app
Real-Time
Basic procedures System admin File system I/O monitor System controller architecture Timed loops Inter-process communication RT/Host communication RT/FPGA communication FPGA personalities Interrupts Datalogger (file I/O)
FPGA
Design flow Simulation Inter-process communication RT/host communication Derived clock domain IP blocks FPGA personality
Networking
Get connected Email Web services UDP TCP IP addresses
Site Map
Guides Code examples Procedures Tags LabVIEW block diagram elements Targets Communications All pages
Glossary How to use About
RIO Developer Essentials Guide for Academia

"Streaming" communication

Queue
RT code

Use a queue to send messages and data between two or more parallel process loops contained within a VI or other VIs. Queues also serve as the foundation for the "Queued State Machine" design pattern.

Channel wire
RT code

Use a channel wire to communicate between two (or more) parallel process loops contained within the same VI, and use a channel wire to stop parallel loops with one "stop" button. Requires LabVIEW 2016 or later version.
Efficiently transfer blocks of data between the RT and PC by network streams.
Efficiently transfer blocks of data between the RT and FPGA by direct memory access (DMA) first-in first-out (FIFO) buffers.
Efficiently transfer blocks of data between the PC and FPGA by direct memory access (DMA) first-in first-out (FIFO) buffers.