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FPGA procedure

Make your first FPGA application

Follow along with this step-by-step tutorial to make a "hello, world!"-like application to experience the advantages of multiple linked VIs running simultaneously on the FPGA target, real-time (RT) target, and desktop computer: (1) "FPGA Main" VI blinks the onboard LEDs and reads the onboard button; these onboard devices physically connect to the FPGA I/O pins, (2) "FPGA testbench" VI runs on the desktop computer for interactive development and debugging of "FPGA Main" in simulation mode prior to compiling to a bitstream file, (3) "RT Main" VI runs as the RT target start-up VI; it runs "FPGA Main", interacts with its front-panel controls/indicators, and communicates with an external desktop computer via network-published shared variables, and (4) "PC Main" VI runs on the desktop computer as a user-friendly human-machine interface (HMI) for remote command and control of "FPGA Main" through the network.

https://youtu.be/uRWhGq7UN74 (31:07)

Code from the video: quickstart_fpga.zip

Procedure

Step 1 of 9: Create a new LabVIEW project

  1. Start LabVIEW
  2. Create a new empty project and save it as “first FPGA application”
  3. Add the Academic RIO Device

Step 2 of 9: Create the FPGA VI to run on the FPGA target

  1. Create a new VI under the FPGA target
  2. Save the VI as “FPGA Main.vi”
  3. Open the block diagram of “FPGA Main”
  4. Change the icon name to “FPGA Main”
  5. Insert code for Process #1:
    • Read the onboard push button state and front-panel “pause” button as the oscillator enable
    • Write onboard LED2 as the oscillator output
    • Write onboard LED3 as the complement of the oscillator output
    • Write onboard LED1 as the paused state
    • Indicate paused and LED states on the front panel
    • Vary the blink rate with a front-panel control
  6. Insert code for Process #2:
    • Blink LED0 once per second

Step 3 of 9: Create the FPGA testbench VI for interactive simulation

  1. Create a new VI under “My Computer”
  2. Save the VI as “FPGA testbench.vi”
  3. Open the block diagram of “FPGA testbench”
  4. Change the icon name to “FPGA testbench”
  5. Insert code:
    • Read front-panel controls that correspond to the “FPGA Main” front-panel controls “pause” and “loop time”
    • Read front-panel control that corresponds to the FPGA input for the onboard button
    • Use the “Desktop Execution Node” to operate the “FPGA Main” front-panel controls and to read its front-panel indicators
    • Write front-panel indicators that correspond to the “FPGA Main” front-panel indicators
    • Update once every 100ms; each update corresponds to 1 system clock cycle on the FPGA

Step 4 of 9: Interactively test and debug FPGA VI

  1. Select the FPGA execution mode as “Simulation”
  2. Run “FPGA testbench” and confirm proper operation of “FPGA Main”
  3. Debug “FPGA Main” until it works properly

Step 5 of 9: Compile the FPGA VI to a bitstream file

  1. Run the VI to automatically create a build specification and to start the compile process

Step 6 of 9: Create and deploy the network-published shared variables (NPSVs)

  1. Create the variable “LEDa” under the Academic RIO Device target
  2. Select “Network-Published” as the variable type
  3. Select “Boolean” as the data type
  4. Repeat for the remaining Boolean variables: LEDb, pause, paused, and stop
  5. Create the variable “loop time” as U32 data type
  6. Save the library as “first FPGA app”
  7. Register IP address of the Academic RIO Device
  8. Deploy the shared variables to the Academic RIO Device so that they persist across power cycles
  9. Confirm that the variables are visible on the network using the “Distributed System Manager” tool

Step 7 of 9: Create the RT VI to run on the real-time target

  1. Create a new VI under the Academic RIO Device target
  2. Save the VI as “RT Main.vi”
  3. Open the block diagram of “RT Main”
  4. Change the icon name to “RT Main”
  5. Insert code:
    • Initialize the “loop time”, “paused”, and “stop” shared variables
    • Open a reference to the “FPGA Main” VI and run it on the FPGA target
    • Write the “FPGA Main” VI front-panel controls “loop time” and “pause” according to the corresponding values in the shared variables
    • Read the “FPGA Main” VI front-panel indicators (LEDs and paused state) and update the corresponding shared variables
    • Loop until “stop” button is clicked
    • Close the reference to the “FPGA Main” VI and reset the FPGA target
  6. Test and debug the code until it works properly

Step 8 of 9: Create the PC human-machine interface (HMI) VI (PC host)

  1. Create a new VI under “My Computer”
  2. Save the VI as “PC Main.vi”
  3. Open the block diagram of “PC Main”
  4. Change the icon name to “PC Main”
  5. Insert code:
    • Place controls and indicators, one for each shared variable
    • Bind the controls and indicators to the shared variables; use the “Shared Variable | Front Panel Binding Mass Configuration” tool to do all at once or select the “Data Binding” property for each control/indicator
    • Idle loop with an event structure that stops when the “Stop Button” is clicked
  6. Run “RT Main” to start the FPGA VI
  7. Run “PC Main” and confirm that “RT Main” (and consequently “FPGA Main”) can be remotely controlled through the network by the HMI running on the desktop computer
  8. Stop “PC Main”; the “RT Main” VI should still be running
  9. Run “PC Main” again; it should resume contact with “RT Main” and be able to control it remotely

Step 9 of 9: Set “RT Main” as the start-up VI

  1. Create a new build specification for a “Real-Time Application”
  2. Enter the name of the build specification
  3. Select “RT Main” as the start-up VI
  4. Build the application
  5. Select “Run as startup”
  6. Restart the Academic RIO Device and confirm that the VI runs properly (LEDs blink, button works) shortly after the Device finishes booting up
  7. Run “PC Main” and confirm that “RT Main” (and consequently “FPGA Main”) can be remotely controlled through the network by the HMI running on the desktop computer