Home
Quickstart Guide
Introduction RIO Academic RIO Application examples Your first RT app Your first FPGA app
Real-Time
Basic procedures System admin File system I/O monitor System controller architecture Timed loops Inter-process communication RT/Host communication RT/FPGA communication FPGA personalities Interrupts Datalogger (file I/O)
FPGA
Design flow Simulation Inter-process communication RT/host communication Derived clock domain IP blocks FPGA personality
Networking
Get connected Email Web services UDP TCP IP addresses
Site Map
Guides Code examples Procedures Tags LabVIEW block diagram elements Targets Communications All pages
Glossary How to use About
RIO Developer Essentials Guide for Academia

"Human-machine interface" tag

Screenshot of LabVIEW VI block diagram and front panels of 'RT Main' and 'PC Main'

Make your first RT application
RT procedure

Follow along with this step-by-step tutorial to make a "hello, world!"-like application to experience the advantages of multiple linked VIs running simultaneously on the real-time (RT) target and desktop computer: (1) "RT Main" runs as the RT target start-up VI, blinks the onboard LEDs, and reads the onboard button; these onboard devices physically connect to the FPGA I/O pins which are accessed with the Academic RIO Device Toolkit Express VIs and default FPGA personality, and (2) "PC Main" VI runs on the desktop computer as a user-friendly human-machine interface (HMI) for remote command and control of "RT Main" through the network via shared variables hosted on the RT target.

Screenshot of LabVIEW VI block diagram and front panel of 'FPGA Main'

Make your first FPGA application
FPGA procedure

Follow along with this step-by-step tutorial to make a "hello, world!"-like application to experience the advantages of multiple linked VIs running simultaneously on the FPGA target, real-time (RT) target, and desktop computer: (1) "FPGA Main" VI blinks the onboard LEDs and reads the onboard button; these onboard devices physically connect to the FPGA I/O pins, (2) "FPGA testbench" VI runs on the desktop computer for interactive development and debugging of "FPGA Main" in simulation mode prior to compiling to a bitstream file, (3) "RT Main" VI runs as the RT target start-up VI; it runs "FPGA Main", interacts with its front-panel controls/indicators, and communicates with an external desktop computer via network-published shared variables, and (4) "PC Main" VI runs on the desktop computer as a user-friendly human-machine interface (HMI) for remote command and control of "FPGA Main" through the network.

LabVIEW PC block diagram: producer-loop contains event structure and guard clause; consumer-loop contains guard clause and case structure; both loops share the same queue reference

Event-driven producer-consumer state machine
PC code

Create a responsive user interface based on two loops operating in parallel: the "producer" loop event structure responds immediately to user interactions such as button clicks and mouse movements that send commands through a queue to the "consumer" loop which performs the required tasks. Separating the state machine into two loops allows the user interface to remain responsive should a consumer task require an unusual amount of time or must wait for a shared resource to become available.