RIO Developer Essentials Guide for Academia
FPGA PC guide
FPGA programming: Simulation techniques
Run the VI with simulated I/O or create a testbench on the PC host to apply a test sequence as the FPGA VI input and monitor the resulting output sequence.
Summary
Compiling the LabVIEW FPGA VI to a bitstream file requires at least 5 minutes whereas simulating the VI on the desktop takes no time at all. Run the VI with simulated I/O (random values) or create a testbench on the PC host to apply a test sequence as the FPGA VI input and monitor the resulting output sequence.
Guides
- Simulate an FPGA VI with the “Simulated I/O” execution mode; the VI runs on the desktop and all of the usual debugging tools such as breakpoints and probes are available.
Code examples
- Create a testbench on the PC host using the “Desktop Execution” node; the PC VI interacts with the FPGA VI in simulation mode to apply a test sequence as the FPGA VI input and monitor the resulting output sequence.