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RIO Developer Essentials Guide for Academia

"Custom FPGA" tag

Develop an FPGA VI
FPGA guide

Develop your own FPGA-targeted VI to take advantage of the unique capabilities of the FPGA target such as high-speed I/O, precision I/O timing, parallel processing, and functionality not offered by the RT processor and Academic RIO Device Toolkit default personality; you can also augment the default personality with your needed capability.
Run the VI with simulated I/O or create a testbench on the PC host to apply a test sequence as the FPGA VI input and monitor the resulting output sequence.
Reuse (import) VHDL code and configure Xilinx IP blocks as drop-in components on the LabVIEW block diagram.