Use a derived clock domain to effectively speed up or slow down the FPGA's 40-MHz clock for a selected portion of the FPGA block diagram.
Operate a portion of FPGA code at a slower clock rate to eliminate cumbersome loop timers and delay mechanisms
Match a portion of FPGA code to the timing requirements of an external peripheral device
Speed up a portion of FPGA code
Easy to define one or more derived clocks to be associated with single-cycle timed loops (SCTLs)
Enter the desired clock frequency and LabVIEW identifies the closest matching frequency that can be obtained as the ratio of two whole numbers times 40MHz
Derived clock frequencies can be defined up to 800MHz (20x speedup) and as low as 4.7 MHz
Keep in mind
Single-cycle timed loops (SCTLs) require the entire loop code to execute in one clock cycle; this is 25ns for the default 40MHz clock. Keep your code lean and eliminate nondeterministic structures, especially if you intend to use a higher-frequency clock domain.
LabVIEW block diagram elements
Locate these elements with "Quick Drop" (press Ctrl+Space and start typing the name); click on an icon to see more sample code that uses that element:
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