Derived clock domains

Use a derived clock domain to effectively speed up or slow down the FPGA's 40-MHz clock for a selected portion of the FPGA block diagram.

Use cases

Operate a portion of FPGA code at a slower clock rate to eliminate cumbersome loop timers and delay mechanisms
Match a portion of FPGA code to the timing requirements of an external peripheral device
Speed up a portion of FPGA code

Features

Easy to define one or more derived clocks to be associated with single-cycle timed loops (SCTLs)
Enter the desired clock frequency and LabVIEW identifies the closest matching frequency that can be obtained as the ratio of two whole numbers times 40MHz
Derived clock frequencies can be defined up to 800MHz (20x speedup) and as low as 4.7 MHz

Keep in mind

Single-cycle timed loops (SCTLs) require the entire loop code to execute in one clock cycle; this is 25ns for the default 40MHz clock. Keep your code lean and eliminate nondeterministic structures, especially if you intend to use a higher-frequency clock domain.

LabVIEW block diagram elements

Locate these elements with "Quick Drop" (press Ctrl+Space and start typing the name); click on an icon to see more sample code that uses that element:

Example code

Connect your Academic RIO Device to your PC using USBLAN, Ethernet, or Wi-Fi. NOTE: Not all Academic RIO Devices have Ethernet and Wi-Fi connectivity options.
Download and unpack the fpga_derived-clock-domains.zip (for use with NI myRIO 1900) or the NIELVISIII-fpga_derived-clock-domains.zip (for use with NI ELVIS III) archive, and then double-click the ".lvproj" file to open the project. NOTE: This project was written for a NI myRIO 1900 or NI ELVIS III connected by USBLAN at IP address 172.22.11.2. If you are using a different IP address or another Academic RIO Device (Example: NI myRIO 1950 or NI RIO Control Module) do the following:
- If using the NI myRIO 1950 or NI RIO Control Module start with the NI myRIO 1900 Archive.
- Different IP address: Right-click on the "NI myRIO 1900" Device, choose "Properties", and then enter the new IP address
- Different device:
  - Right-click on the top of the project hierarchy, select "New Targets and Devices", keep the "Existing target or device" option, and then find and select your particular device
  - Select all of the components under the "NI myRIO 1900" device: click the first one and then shift+click the last one
  - Drag the selected components to the new device
  - Right-click the "NI myRIO 1900" device and select "Remove from project"
Run the “FPGA Main” VI and observe the Academic RIO Device onboard LEDs. Each LED is driven by identical oscillators but located in three different clock domains:
- LED0: 40MHz default clock domain (1Hz blink frequency)
- LED1: 80MHz derived clock domain (2Hz blink frequency)
- LED2: 10MHz derived clock domain (0.25Hz blink frequency)
Stop the VI by clicking the “Abort” button.

Expected results

https://youtu.be/UT3G_wr6V0E (0:46)

Developer walk-through

https://youtu.be/1BBZLZMPjRs (2:15)

Outline

Review overall structure
- Three identical single-cycle timed loops (SCTLs) containing a 50% duty cycle 1-Hz oscillator (based on 40 MHz clock) connected to an LED
- Loop #1 uses the default 40-MHz clock
- Loop #2 uses a derived 80-MHz clock to create a 2-Hz oscillator
- Loop #3 uses a derived 10-MHz clock to create a 0.25-Hz oscillator
Create a derived clock
Select the SCTL clock source

FPGA code example