FPGA/RT and FPGA/host inter-target communication

Transfer data, commands, and status between the FPGA target and a host system (RT or PC).

Diagram showing communication pathways between PC host, RT target, and FPGA target

Summary

Inter-target communication refers to data exchanges between a target (FPGA or RT) and a host computer (RT or desktop PC):
- FPGA/RT communication: RT serves as host to the FPGA target
- RT/PC communication: PC serves as host to the RT target
Two methods are available for the FPGA target:
- Programmatic front-panel communication (tag, latest value)
- Direct memory access (DMA) (message, streaming, buffered)

The host system operates the FPGA VI front panel control by “remote control,” so to speak, and reads the FPGA VI indicators
The host system transfers one set of front panel control “touches” and indicator reads for each call of the “Read/Write Control” node
Suitable for small, frequent data transfers where relatively low throughput rate is acceptable; for example, the host could:
- adjust FPGA configuration parameters
- read FPGA status or a single data measurement
- initiate an FPGA process
Relatively low setup overhead per call, but relatively high CPU usage per call
Known as “tag-based” (latest value) communication: values that change on the FPGA target in between host data transfers are completely missed by the host

The host operating system sets up a data transfer of a relatively large block of data, and then proceeds with other tasks as the data transfers directly from the FPGA to a block of memory on the host device
Suitable for high-throughput transfer, e.g., audio and waveform streaming
Relatively high setup overhead per call, but relatively low CPU usage while the transfer is in progress – most efficient for infrequent transfer of large blocks of data
May also be used for passing command and status messages where every value must be reliably transferred
Known as streaming, message, and buffered communication: values transfer through a first-in first-out (FIFO) buffer and are guaranteed to reach the host provided that the buffer is not allowed to overflow
FIFOs are unidirectional, i.e., one FIFO is required to transfer from the FPGA to the host and a second FIFO is required to transfer to the FPGA from the host

Transferring Data between the FPGA and Host (FPGA Module) (http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpgaconcepts/fpga_data_transfer_overview)
Describes programmatic front-panel communication and direct memory access (DMA) communication.