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FPGA PC code example

Stream high-speed data between FPGA and PC with a DMA FIFO

Efficiently transfer blocks of data between the PC and FPGA by direct memory access (DMA) first-in first-out (FIFO) buffers.

LabVIEW PC block diagram snippet: Read an audio frame from FPGA DMA FIFO, process the frame, and write the processed frame back to the FPGA

Use cases


Keep in mind

LabVIEW block diagram elements

Locate these elements with "Quick Drop" (press Ctrl+Space and start typing the name); click on an icon to see more sample code that uses that element:

Open FPGA VI Reference
Read-Write Control
Invoke Method
Close FPGA VI Reference
FIFO Method Node
Join Numbers
Split Number
Loop Timer

Example code

Expected results

https://youtu.be/AW8RQlkIVeo (5:16)

Developer walk-through

https://youtu.be/SzeTRC-w7aA (6:42)


For more information

  1. Transferring Data between the FPGA and Host (FPGA Module) (http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpgaconcepts/fpga_data_transfer_overview)
    Describes direct memory access (DMA) communication and compares it to programmatic front-panel communication.