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RIO Developer Essentials Guide for Academia

"Inter-target communication" tag

Diagram of NI myRIO architecture showing RT and FPGA targets, communication subsystems (USBLAN and wireless), file system, I/O, and onboard devices

NI Academic RIO Device architecture overview
RIO guide

A high-level overview of the Academic RIO Device architecture and features.

PC and RIO block diagram with FPGA target highlighted

Develop an FPGA VI
FPGA guide

Develop your own FPGA-targeted VI to take advantage of the unique capabilities of the FPGA target such as high-speed I/O, precision I/O timing, parallel processing, and functionality not offered by the RT processor and Academic RIO Device Toolkit default personality; you can also augment the default personality with your needed capability.

Diagram showing communication pathway between PC host and RT target

RT/host inter-target communication
RT guide PC guide

Transfer data, commands, and status between the RT target and a host system.

LabVIEW FPGA block diagram snippet: RT VI operates the FPGA front panel

Programmatic front-panel communication with RT
FPGA code RT code

The RT VI operates (writes) the front-panel controls of the FPGA VI and reads its indicators.

LabVIEW RT block diagram snippet: RT and PC read and write the same network-published shared variables

Network-published shared variable (NPSV)
RT code PC code

A network-published shared variable (NPSV) behaves like a global variable that links process loops residing in two or more network-connected targets.

LabVIEW RT block diagram snippet: RT opens a handle to a network-published shared variable and reads its value

Programmatically access a network-published shared variable (NPSV)
RT code PC code

Use the NPSV programmatic API (application programmer's interface) VIs as an alternative method to a shared variable node.

LabVIEW RT block diagram snippet: PC writes one element to a network stream channel, RT reads the element from the same channel

Send messages through a network stream channel
RT code PC code

Send command and status messages through a low-latency lossless network-based data communication channel between the RT target and PC host system.

LabVIEW RT block diagram snippet: RT writes blocks of data to a network stream channel, PC reads the blocks from the same channel

Stream high-speed data through a network stream channel
RT code PC code

Efficiently transfer blocks of data between the RT and PC by network streams.

LabVIEW RT block diagram snippet: Read an audio frame from FPGA DMA FIFO, process the frame, and write the processed frame back to the FPGA

Stream high-speed data between FPGA and RT with a DMA FIFO
FPGA code RT code

Efficiently transfer blocks of data between the RT and FPGA by direct memory access (DMA) first-in first-out (FIFO) buffers.

Diagram showing communication pathways between PC host, RT target, and FPGA target

FPGA/RT and FPGA/host inter-target communication
FPGA guide RT guide PC guide

Transfer data, commands, and status between the FPGA target and a host system (RT or PC).

LabVIEW FPGA block diagram snippet: PC VI operates the FPGA front panel

Programmatic front-panel communication with PC
FPGA code PC code

The PC VI operates (writes) the front-panel controls of the FPGA VI and reads its indicators.

LabVIEW PC block diagram snippet: Read an audio frame from FPGA DMA FIFO, process the frame, and write the processed frame back to the FPGA

Stream high-speed data between FPGA and PC with a DMA FIFO
FPGA code PC code

Efficiently transfer blocks of data between the PC and FPGA by direct memory access (DMA) first-in first-out (FIFO) buffers.