Quickstart Guide
Introduction RIO Academic RIO Application examples Your first RT app Your first FPGA app
Basic procedures System admin File system I/O monitor System controller architecture Timed loops Inter-process communication RT/Host communication RT/FPGA communication FPGA personalities Interrupts Datalogger (file I/O)
Design flow Simulation Inter-process communication RT/host communication Derived clock domain IP blocks FPGA personality
Get connected Email Web services UDP TCP IP addresses
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RIO Developer Essentials Guide for Academia
RIO guide

NI Academic RIO Device architecture overview

A high-level overview of the Academic RIO Device architecture and features.

Diagram of NI myRIO architecture showing RT and FPGA targets, communication subsystems (USBLAN and wireless), file system, I/O, and onboard devices


RT target features

FPGA target features