1. Introduction and software setup

• Resources available
• Navigation tips
• Intended audience
• Learning objectives
• Additional resources

2. RIO

• Fast facts
• RT (real-time) target
• FPGA (field-programmable gate array) target
• How does RIO LabVIEW programming compare to the desktop environment?
• RIO embedded control and monitoring applications

3. Academic RIO Device

• Fast facts
• Platforms and features
• Architecture
• NI Academic RIO Device Toolkit and default FPGA personality

4. Browse application examples

• Home security system with remote user interface
• Real-time audio processor
• Headless datalogger (file I/O)
• Remote webcam photo logger
• High-precision waveform measurement
• Web services (calling and hosting)
• Networking and IoT (TCP, UDP)

5. Make your first RT application

• Make a "hello, world!"-like application to experience the advantages of multiple linked VIs running simultaneously on the real-time (RT) target and desktop computer
• "RT Main" VI -- runs as the RT target start-up VI, blinks the onboard LEDs, reads the onboard button, and communicates with an external desktop computer via network-published shared variables
• "PC Main" VI -- runs on the desktop computer as a user-friendly human-machine interface (HMI) for remote command and control of "RT Main" through the network

6. Make your first FPGA application

• Make a "hello, world!"-like application to experience the advantages of multiple linked VIs running simultaneously on the FPGA target, real-time (RT) target, and desktop computer
• "FPGA Main" VI -- blinks the onboard LEDs and reads the onboard pushbutton
• "FPGA testbench" VI -- runs on the desktop computer for interactive development and debugging of "FPGA Main" in simulation mode prior to compiling to a bitstream file
• "RT Main" VI -- runs as the RT target start-up VI; it runs "FPGA Main", interacts with its front-panel controls/indicators, and communicates with an external desktop computer via network-published shared variables
• "PC Main" VI -- runs on the desktop computer as a user-friendly human-machine interface (HMI) for remote command and control of "FPGA Main" through the network

Basic procedures

• Make a new RT LabVIEW project
• Add I/O with the Academic RIO Device Toolkit and default FPGA personality
• Deploy the project as the start-up VI

System administration

• Set the administrator password
• Set the system time and date with a web browser, NI MAX, or PC host VI
• Manage the installed software set add-ons

File system

View the Academic RIO Device file system through a web browser or mount it as a drive on your host system

I/O monitor

Interactively set output values and monitor input values on the Academic RIO Device MXP and MSP connector signals to quickly test your connected peripheral devices without creating a VI

System controller architecture

• Based on industry-standard model for embedded control and monitoring applications
• "Queued Message Handler" with multiple process loops
• "Queued State Machine" implements process loop behavior
• "Event-driven Producer-Consumer State Machine" as PC host user interface

Timed loops

Timed loops execute at a user-specified rate -- particularly useful for process control loops.

• Implement a precision timed loop
• Measure loop time

Inter-process communication

Exchange data between parallel process loops, especially between deterministic (timed) and nondeterministic (conventional) loops.

• Deterministic / non-deterministic process loops: single-element shared process variable and channel wire
• Non-deterministic process loops: local and global variables, single-process shared process variable (SPSV), functional global variable (FGV), queue, and channel wire

RT/Host communication

RT communicates with the PC host VI or other network-capable device through the Academic RIO Device network connection.

• Access a network-published shared variable
• Send command and status messages through a network stream channel
• Stream high-speed data through a network stream channel
• Use Internet protocols such as UDP, TCP/IP, HTTP, and WebDAV

RT/FPGA communication

• Read and write the FPGA VI indicators and controls
• Stream high-speed data through a DMA FIFO (direct memory access first-in first-out buffer)

Interrupts

• Trigger a process ("callback VI") to run immediately on an external event such as a digital input transition or an analog input voltage threshold crossing
• Trigger a process to run when an FPGA-based timer generates an interrupt request (IRQ)

FPGA personalities

The FPGA "personality" (bitstream file) determines how the RT target interacts with peripheral devices. The personality can also implement custom functionality.

• Add basic I/O with the Academic RIO Device Default Personality
• Add enhanced I/O with the Academic RIO Device High-Throughput Personality
• Augment (modify) the Academic RIO Device Default Personality with your own code

Headless datalogger (file I/O)

• Log measurements to a file on the USB thumbdrive
• Read a configuration text file

Queue-based state machines

Queue-based state machines excel at implementing system control, data measurement and processing, and other tasks to respond to inputs from the surrounding physical system and user interface. Popular design patterns include:

• Queued state machine (QSM) for specific tasks
• Queued message handler (QMH) for system-level application
• Event-driven producer-consumer loops for PC-based human-machine interface (HMI) to the RT application

Get connected

• Connect to a consumer-grade wireless router for Internet access
• Create an ad-hoc wireless network
• Create a wired (Ethernet) network with PC

Email

Send email (including attached files) and text messages from the Academic RIO Device.

Web services

Use the infrastructure of the Web for machine-to-machine exchange of information. The Academic RIO Device can call Web services to retrieve information and can also host Web services to provide information to other systems.

UDP networking

UDP is a simple and efficient connectionless IP networking protocol used between LabVIEW applications as well as other IoT devices.

• Send and receive messages
• Client-server model for control and monitoring

TCP networking

TCP is a reliable connection-based IP networking protocol used between LabVIEW applications as well as other IoT devices.

• Send and receive messages
• Client-server model for control and monitoring
• Synchronize system clock to NIST time source
• Check for Internet access

IP addresses

• Show available IP addresses on PC host or RT target
• Learn my public Internet IP address by calling a Web service

FPGA design flow

Learn how to develop an FPGA VI: create a new FPGA LabVIEW project, simulate the VI to verify functionality, compile the VI to a bitfile, and deploy the project as the start-up VI.

Simulation and testbenching

Run the VI with simulated I/O or create a testbench on the PC host to apply a test sequence as the FPGA VI input and monitor the resulting output sequence.

Inter-process communication

Exchange data between parallel process loops using local and global variables.

FPGA/RT and FPGA/Host communication

• Read and write the FPGA VI indicators and controls
• Stream high-speed data through a DMA FIFO (direct memory access first-in first-out buffer)

Derived clock domains

Speed up or slow down a process loop time from the base 40-MHz clock

IP blocks

Reuse (import) VHDL code and configure Xilinx IP blocks as drop-in components on the LabVIEW block diagram.

FPGA personality

Augment (modify) the Academic RIO Device Default FPGA "personality" (bitstream file) with your own block diagram code.