The Academic RIO Device Toolkit subVI “Set Custom Bitfile” must be called immediately after opening the reference to the FPGA VI – this alerts the RT target to the presence of FPGA functions that correspond to the Device Toolkit Express VIs and low-level VIs
The default Device personality consumes the majority of FPGA resources; it may be necessary to carefully remove some of the existing functions to make room for your own functions
The default Device personality VI code that drives the I/O pins is rather involved due to the shared pins, e.g., the PWM output can also be a general-purpose digital input/output. myRIO Only: Consider using the MSP C-connector for any custom FPGA functions that must access FPGA I/O instead of the MXP A and B connectors.
LabVIEW block diagram elements
Locate these elements with "Quick Drop" (press Ctrl+Space and start typing the name); click on an icon to see more sample code that uses that element:
Connect your Academic RIO Device to your PC using USBLAN, Ethernet, or Wi-Fi. NOTE: Not all Academic RIO Devices have Ethernet and Wi-Fi connectivity options.
If using the NI myRIO 1950 or NI RIO Control Module start with the NI myRIO 1900 Archive.
Different IP address: Right-click on the "NI myRIO 1900" Device, choose "Properties", and then enter the new IP address
Right-click on the top of the project hierarchy, select "New Targets and Devices", keep the "Existing target or device" option, and then find and select your particular device
Select all of the components under the "NI myRIO 1900" device: click the first one and then shift+click the last one
Drag the selected components to the new device
Right-click the "NI myRIO 1900" device and select "Remove from project"
Run the “RT Main” VI to load an augmented Academic RIO Device FPGA personality to measure the positive-pulse width of the periodic pulse waveform applied to the MSP (C-connector) digital input on DIO0
The RT code generates three periodic pulse waveforms on the digital outputs of the MXP A-connector/Bank A that you can connect with a wire to C/DIO0 / B/DIO0 on NI ELVIS III:
A/PWM0, pin 27 – Pulse-width modulated (PWM) output; the PWM signal is generated on the FPGA fabric itself from the same default 40-MHz system clock used by the pulse-width measurement system, therefore you should observe zero jitter as you adjust the duty cycle of the PWM waveform
A/DIO0, pin 11 – Pulse generated within a conventional (non-deterministic) while-loop structure that contains a 10-ms delay element; set the meter display limits to 9.5ms and 10.5ms to more clearly see the jitter
A/DIO1, pin 13 – Pulse generated within a timed (deterministic) while-loop structure that contains a 10-ms delay element; observe that there is still some degree of jitter, but much less than with a conventional while loop
The FPGA also generates a 1-kHz square wave on digital output C/DIO1 / B/DIO0 on NI ELVIS III.