myRIO Custom FPGA Project

You can use the myRIO Custom FPGA Project template as a starting point for creating myRIO applications with your custom FPGA code. With the myRIO Custom FPGA Project template, you can easily modify the code of the myRIO shipping FPGA personality.

This template is suitable for applications that have the following characteristics:

• Contain multiple time-critical elements that need to run in parallel.
• Require more precise timing than the myRIO RT controller can achieve.
• Use a type of I/O that is not available with the myRIO shipping FPGA personality.

The following example applications can benefit from the use of this template:

• A check engine auto scanner that supports the CAN protocol.
• An audio effects generator that analyzes an audio sample and simultaneously generates multiple effects.

Table of Contents

System Requirements

Understanding the Components of This Template

Running This Template

Modifying This Template

Related Information

Development System

• LabVIEW Full or Professional Development System
• LabVIEW Real-Time Module
• LabVIEW FPGA Module
• Xilinx compilation tools for Vivado
• LabVIEW myRIO Toolkit

Use the LabVIEW FPGA Module to create custom FPGA code. Use the myRIO VIs and the LabVIEW Real-Time Module to create real-time (RT) code. The FPGA code and the RT code run in parallel.

Hardware

• myRIO

This template consists of the following VIs:

• FPGA Main Default.vi/FPGA High Throughput.vi—Contains the myRIO shipping FPGA personality. This VI compiles and runs on the myRIO FPGA target. You can modify this VI to suit your application needs. NI recommends that you only add new FPGA code to this VI and do not modify the existing code. This VI might not correctly work with the myRIO VIs if you modify the existing code.
  
  Note  NI provides two types of myRIO FPGA personalities: default FPGA personality and high-throughput FPGA personality. By default, you can use the default FPGA personality with the myRIO Toolkit. Visit ni.com/info and enter the Info Code ex6g5a to learn more about how to use the high-throughput FPGA personality.
  
  
• RT Main.vi—Contains the main myRIO application. This VI performs the following tasks:
  • Downloads the code from the FPGA Main Default VI/FPGA High Throughput VI to the myRIO FPGA target and runs the code.
  • Sets the custom FPGA reference so that the myRIO VIs can work with the custom FPGA code.
  • Acquires and processes data from the user button on the myRIO and accesses any custom FPGA I/O.

The RT Main VI in this template uses a Flat Sequence structure that executes frames from left to right:

The Flat Sequence structure in this template executes the following frames from left to right:

1. Initialize myRIO with custom FPGA—Initializes the application. Use this frame to open and set the custom FPGA bitfile that the FPGA Main Default VI/FPGA High Throughput VI generates. You can also use this frame to initialize the myRIO, variables, and user interface elements, such as controls and indicators.
2. Acquire and process data—Acquires data from the myRIO and processes the data for presentation. The While Loop repeats code until you click Stop or an error occurs. You can use the myRIO VIs or the LabVIEW FPGA host interface in this frame. Use the myRIO VIs to access any myRIO default functionality. Use the FPGA host interface for any custom elements that you add to the FPGA Main Default VI/FPGA High Throughput VI.
3. Close—Closes and resets the custom FPGA code. You can also use this frame to close user interface elements and variables before the application exits.

1. In the Project Explorer window, navigate to your myRIO FPGA target to find the FPGA Main Default VI/FPGA Main High Throughput VI.
2. Right-click the FPGA Main Default VI/FPGA Main High Throughput VI and select Create Build Specification from the shortcut menu. Verify that FPGA Main Default/FPGA Main High Throughput appears under Build Specifications.
3. Select File»Save to save the specification to the LabVIEW project.
4. Right-click FPGA Main Default/FPGA Main High Throughput under Build Specifications and select Build from the shortcut menu to display the Select Compile Server dialog box.
5. Click OK to generate the custom FPGA bitfile.
6. Open and run the RT Main VI.
7. Press the user button on the myRIO and observe the state change of the Button Value indicator.
8. Click Stop to stop the application.

The following table summarizes the design decisions you must make when modifying this template.

Controlling the Order of Execution

This template uses the Flat Sequence structure to control data flow. The data leaves each frame as the frame finishes executing. This template uses the Flat Sequence structure to demonstrate the purpose of the code in each frame.

Note  Do not overuse the Flat Sequence structure for controlling the execution order because the Flat Sequence structure prohibits parallel operations.

When you modify this template, you can remove the Flat Sequence structure and establish data dependency between nodes. For example, wiring the error in and error out clusters through nodes controls the data to flow from one node to another.

Adding Initialization Code

This template initializes the FPGA bitfile that the FPGA Main Default VI/FPGA Main High Throughput VI generates. If you want to use your custom FPGA personality, you must open and set the custom FPGA bitfile. Otherwise, the myRIO uses the shipping FPGA personality. You also can initialize the data to specific values or to open a file for logging.

Modifying the Data Acquisition and Processing Code

This template uses the Button Express VI to acquire user button data from the myRIO and displays the button value on a Boolean indicator.

You can add code to acquire data from the myRIO and process the data based on your application needs. Use the myRIO VIs to access myRIO I/O channels and the onboard devices. Add time-critical functions to your FPGA code and use the FPGA host interface to access the custom elements that you add to the FPGA code. Adding time-critical functions to your FPGA code allows the FPGA functions and RT functions to run in parallel at a fast rate.

Adding Closing Code

This template uses the Close FPGA VI Reference function to close the reference to the FPGA Main Default VI/FPGA Main High Throughput VI. You must close the FPGA reference to reset the FPGA target at the end of the application.

You can add code that executes after the data acquisition and processing completes but before the application exits. Closing code commonly accomplishes the following tasks:

• Frees memory by closing any open references
• Flushes any buffers in use
• Resets the myRIO

Modifying Error Handling

By default, if an error occurs in the Button Express VI, this template stops. If you do not want the error to stop your application, you can remove the OR function and wire the Stop control directly to the conditional terminal of the While Loop. The error in and error out clusters pass error information from the beginning of the VI to the end and report the error at the end of the execution flow.

Refer to the LabVIEW Help, available by selecting Help»LabVIEW Help from LabVIEW, for information about LabVIEW concepts or objects used in this sample project. You also can use the Context Help window to learn basic information about LabVIEW objects as you move the cursor over each object. To display the Context Help window in LabVIEW, select Help»Show Context Help.

If you use the myRIO high-throughput FPGA personality, refer to the Voice Recorder sample project, available from the Create Project dialog box, for an example of adapting this template to an audio sampling application.

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