Quickstart Guide
Introduction RIO Academic RIO Application examples Your first RT app Your first FPGA app
Basic procedures System admin File system I/O monitor System controller architecture Timed loops Inter-process communication RT/Host communication RT/FPGA communication FPGA personalities Interrupts Datalogger (file I/O)
Design flow Simulation Inter-process communication RT/host communication Derived clock domain IP blocks FPGA personality
Get connected Email Web services UDP TCP IP addresses
Site Map
Guides Code examples Procedures Tags LabVIEW block diagram elements Targets Communications All pages
Glossary How to use About
RIO Developer Essentials Guide for Academia
FPGA procedure

Modify the default Academic RIO Device FPGA personality

Add your own functionality to the default Academic RIO Device FPGA "personality" (bitfile) to retain selected Device Express VI capabilities.

https://youtu.be/4fM7smWFD_E (3:09)

Code from the video: fpga_modify-default-myrio-personality.zip


  1. Select “File | Create Project” from any LabVIEW VI or project
  2. Select the “myRIO” template filter
  3. Select “myRIO Custom FPGA Project”
  4. Enter the project name and project root folder, select your myRIO device, then click “Finish”
  5. Open the “FPGA Main Default.vi”
  6. Choose “File | Save As” with the “Open additional copy” with “Add copy to .lvproj” option enabled
  7. Use “FPGA Main Modified” as the VI name (keep the existing version in the project)
  8. Make the necessary modification (see Augmented default Academic RIO Device personality for example code)
  9. Test and debug your newly-added code (see Simulate an FPGA VI and “Desktop Execution Node” as an FPGA VI Testbench for simulation techniques)
  10. Right-click on the “FPGA Main Modified.vi” and choose “Create Build Specification”
  11. Right-click on the build spec and choose “Build” (see Compile an FPGA VI for compiling options)
  12. See the Augmented default Academic RIO Device personality code example to learn how to download and run the modified Device personality so that Academic RIO Device Express VIs work properly on the RT target.
IMPORTANT: NI recommends that you do not modify the existing FPGA code, as this code has been designed to work properly with the Academic RIO Device Express VIs and corresponding low-level VIs.