IMPORTANT: NI recommends that you do not modify the existing FPGA code, as this code has been designed to work properly with the Academic RIO Device Express VIs and corresponding low-level VIs.
Save compilation time by carefully removing (commenting out with the “Diagram Disable” structure) blocks of default code that you do not need
Adding FPGA functionality that does not require hardware I/O pins is especially easy; simply place the new code in its own region in the block diagram
The default Academic RIO Device personality VI code that drives the I/O pins is rather involved due to the shared pins, e.g., the PWM output can also be a general-purpose digital input/output. Consider using the MSP C-connector for any custom FPGA functions that must access FPGA I/O instead of the MXP A and B connectors.
Building the default Device FPGA personality bitfile requires about eight or nine minutes with the Xilinx toolchain “Default” setting. You may wish to experiment with other settings that could potentially reduce the compilation time.
The default Device personality consumes the majority of FPGA resources (see the next point); it may be necessary to carefully remove some of the existing functions to make room for your own functions
The unmodified Device default personality uses the following FPGA resources:
Total slices: 99.9% (4395 of 4400)
Slice registers: 38.5% (13556 of 35200)
Slice LUTs: 88.9% (15652 of 17600)
Block RAMs: 8.3% (5 of 60)
DSP48s: 0.0% (0 of 80)
Study the “myRIO Custom FPGA Project Documentation.html” page located in the “Project Documentation” folder of the LabVIEW project for complete details