Right-click the “FPGA Target”, choose “Select Execution Mode”, and then “Simulation (Simulated I/O)”; confirm that the word “Simulation” appears in the FPGA Target label
Run the VI as you normally would
Use any or all of these techniques:
Add temporary front-panel indicators (remember to remove them before compiling as they require FPGA fabric resources)
Probes (can float the probe window next to the signal)
IMPORTANT: FPGA I/O node outputs are not active during simulation; inputs are connected to random number generators. Use the “Desktop Execution” node in a desktop VI to set desired values of the FPGA I/O node outputs.
All of the usual debugging tools for desktop VIs are available in simulation mode
The Single-Cycle Timed Loop (SCTL) behavior is correctly modelled by the simulator