Use cases

• Develop and debug an FPGA VI by applying test patterns to the FPGA inputs and observing the resulting FPGA outputs
• Implement a testbench with the FPGA VI as the “device under test” and the PC VI emulates the external environment of the FPGA, acting as the test pattern generator and monitor
• Apply a known sequence to the FPGA inputs and check whether the FPGA produces the correct output sequence
• Interactively write and read FPGA I/O lines from the PC VI front panel

Features

• The “Desktop Execution” node (DEN) connects to any or all of the FPGA I/O nodes when the FPGA target is in simulation mode
• Similar concept as programmatic front-panel communication in which the PC VI operates the FPGA front-panel controls and reads its indicators
• All of the standard FPGA VI debugging techniques used to simulate an FPGA (execution highlighting, probes, and sampling probes) may be used on the FPGA VI block diagram while the PC VI executes

Keep in mind

• Each time the DEN executes the FPGA system clock advances by a user-defined number of clock ticks (1 tick by default)
• Conventional while-loop structures on the FPGA target require a minimum of three clock ticks per loop iteration
• In contrast, single-cycle timed loops (SCTLs) execute within a single clock tick per iteration
• The FPGA itself is inactive during simulation, i.e., the actual FPGA I/O pins do not change when operated by the DEN

LabVIEW block diagram elements

Locate these elements with "Quick Drop" (press Ctrl+Space and start typing the name); click on an icon to see more sample code that uses that element:

Example code

• Connect your Academic RIO Device to your PC using USBLAN, Ethernet, or Wi-Fi. NOTE: Not all Academic RIO Devices have Ethernet and Wi-Fi connectivity options.
• Download and unpack the fpga-pc_desktop-execution-node.zip (for use with NI myRIO 1900) or the NIELVISIII-fpga-pc_desktop-execution-node.zip (for use with NI ELVIS III) archive, and then double-click the ".lvproj" file to open the project. NOTE: This project was written for a NI myRIO 1900 or NI ELVIS III connected by USBLAN at IP address 172.22.11.2. If you are using a different IP address or another Academic RIO Device (Example: NI myRIO 1950 or NI RIO Control Module) do the following:
  • If using the NI myRIO 1950 or NI RIO Control Module start with the NI myRIO 1900 Archive.
  • Different IP address: Right-click on the "NI myRIO 1900" Device, choose "Properties", and then enter the new IP address
  • Different device:
    • Right-click on the top of the project hierarchy, select "New Targets and Devices", keep the "Existing target or device" option, and then find and select your particular device
    • Select all of the components under the "NI myRIO 1900" device: click the first one and then shift+click the last one
    • Drag the selected components to the new device
    • Right-click the "NI myRIO 1900" device and select "Remove from project"
• Open the “FPGA Main” VI
• Create sampling probes to display the FPGA inputs and outputs as waveforms; add the system clock waveform, too
• Open and run the “PC Main” VI to apply a fixed test pattern to the FPGA input
• Confirm that the two FPGA output lines toggle in response and that they transition on each rising edge of the system clock
• Experiment: Convert the SCTL to a conventional while-loop; the while-loop iteration time is now longer than the PC VI oscillator and misses the transitions; configure the Desktop Execution Node in “PC Main” to increase the number of clock ticks per iteration to 2 and try again

Expected results

Developer walk-through

Outline

• Review overall structure
  • PC Main – for-loop iterates 10 times to toggle “Button0” FPGA I/O node
  • FPGA Main – single-cycle timed loop (SCTL) encloses simple FPGA circuit: connect “Button0” to “LED0” and invert the button signal to drive “LED3”
  • FPGA target must be in simulation mode (see LabVIEW project)
• Configure “Desktop Execution Node”
  • Advances FPGA simulation time by a user-selectable number of clock cycles on each run
  • Writes to FPGA input nodes at the beginning of the clock cycle
  • Reads FPGA output nodes at the end of the clock cycle
• Set up waveform sampling probes
• Use “Wait” function to slow down the simulation, if desired
  • Occasionally useful as a debugging aid

Related content

Tags:

• desktop execution node
• FPGA simulation

Targets:

• FPGA
• PC

Communications:

• inter-target
• FPGA-PC

LabVIEW VIs and block diagram elements:

• Desktop Execution node
• Single-Cycle Timed Loop