If using the NI myRIO 1950 or NI RIO Control Module start with the NI myRIO 1900 Archive.
Different IP address: Right-click on the "NI myRIO 1900" Device, choose "Properties", and then enter the new IP address
Right-click on the top of the project hierarchy, select "New Targets and Devices", keep the "Existing target or device" option, and then find and select your particular device
Select all of the components under the "NI myRIO 1900" device: click the first one and then shift+click the last one
Drag the selected components to the new device
Right-click the "NI myRIO 1900" device and select "Remove from project"
Open the “FPGA Main” VI
Create sampling probes to display the FPGA inputs and outputs as waveforms; add the system clock waveform, too
Open and run the “PC Main” VI to apply a fixed test pattern to the FPGA input
Confirm that the two FPGA output lines toggle in response and that they transition on each rising edge of the system clock
Experiment: Convert the SCTL to a conventional while-loop; the while-loop iteration time is now longer than the PC VI oscillator and misses the transitions; configure the Desktop Execution Node in “PC Main” to increase the number of clock ticks per iteration to 2 and try again