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FPGA PC code example

"Desktop Execution" node as an FPGA VI testbench

The PC VI interacts with the FPGA VI in simulation mode to apply a test sequence as the FPGA VI input and monitor the resulting output sequence.

LabVIEW PC block diagram snippet: PC reads and writes FPGA I/O nodes in simulation mode

Use cases


Keep in mind

LabVIEW block diagram elements

Locate these elements with "Quick Drop" (press Ctrl+Space and start typing the name); click on an icon to see more sample code that uses that element:

Desktop Execution node
Single-Cycle Timed Loop

Example code

Expected results

https://youtu.be/MHXvrZWJoXc (1:48)

Developer walk-through

https://youtu.be/cKwF7tHY0ho (4:27)