RIO Developer Essentials Guide for Academia
FPGA PC code example
Programmatic front-panel communication with PC
The PC VI operates (writes) the front-panel controls of the FPGA VI and reads its indicators.
- Programmatically control the FPGA VI application and monitor its status indicators
- Control and read FPGA I/O lines directly from the host PC
- Easy to code, low overhead, quick response
- Ideal for small, frequent transfers
- Available for RT/FPGA communications, too
Keep in mind
LabVIEW block diagram elements
Locate these elements with "Quick Drop" (press Ctrl+Space and start typing the name); click on an icon to see more sample code that uses that element:
- Connect your Academic RIO Device to your PC using USBLAN, Ethernet, or Wi-Fi. NOTE: Not all Academic RIO Devices have Ethernet and Wi-Fi connectivity options.
Download and unpack the
fpga-pc_programmatic-front-panel-communication.zip (for use with NI myRIO 1900)
NIELVISIII-fpga-pc_programmatic-front-panel-communication.zip (for use with NI ELVIS III)
archive, and then double-click the ".lvproj" file to open the project. NOTE: This project was written for a NI myRIO 1900 or NI ELVIS III connected by USBLAN at IP address 172.22.11.2.
If you are using a different IP address or another Academic RIO Device (Example: NI myRIO 1950 or NI RIO Control Module) do the following:
- If using the NI myRIO 1950 or NI RIO Control Module start with the NI myRIO 1900 Archive.
- Different IP address: Right-click on the "NI myRIO 1900" Device, choose "Properties", and then enter the new IP address
- Different device:
- Right-click on the top of the project hierarchy, select "New Targets and Devices", keep the "Existing target or device" option, and then find and select your particular device
- Select all of the components under the "NI myRIO 1900" device: click the first one and then shift+click the last one
- Drag the selected components to the new device
- Right-click the "NI myRIO 1900" device and select "Remove from project"
- Run the “PC Main” VI:
- PC front panel effectively “clones” the FPGA front panel to control the NI Academic RIO Device onboard LEDs 0 and 3
- PC displays the state of the Device onboard pushbutton, too
- Open and run the “FPGA Main” VI to see the PC VI operate the FPGA VI front panel controls
- Stop the PC VI, and then operate the FPGA VI from its own front panel
- Review overall structure:
- FPGA Main
- Front panel control (LED0) and indicator (Button0) connected to FPGA I/O nodes
- Contained within a perpetual while loop
- PC Main
- Download and run the FPGA bitfile with “Open FPGA VI Reference” function
- “Read/Write Control” function reads desired LED state and writes it to FPGA LED0 control; reads Button0 indicator and displays its value on front panel
- Runs the “Read/Write Control” function once every 100ms until “Stop” button is pressed
- “Close FPGA VI Reference” disconnects from and resets the FPGA VI
- Locate the functions subpalette