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FPGA guide

Develop an FPGA VI

Develop your own FPGA-targeted VI to take advantage of the unique capabilities of the FPGA target such as high-speed I/O, precision I/O timing, parallel processing, and functionality not offered by the RT processor and Academic RIO Device Toolkit default personality; you can also augment the default personality with your needed capability.

PC and RIO block diagram with FPGA target highlighted


Application example

This audio streaming and real-time processing application example illustrates how to create a custom FPGA VI that samples the Academic RIO Device stereo audio input, sends blocks of samples (“audio frames”) to the RT for processing, and plays the processed audio frames on the Device audio output. The FPGA sampling rate defaults to 50-kHZ but can go considerably higher, thanks to the high-speed processing offered by the FPGA target.

Use cases


Design flow procedure

  1. Create a new FPGA project to design an FPGA from scratch, or create a new project to modify the default Academic RIO Device FPGA personality
  2. Design the FPGA VI architecture using one or more of these coding styles:
  3. Simulate the VI and thoroughly debug it to ensure correct functionality before you expend effort compiling the VI
    • Debugging techniques include execution highlighting, breakpoints, and probes
    • Sampling probes provide familiar waveform-based views of activity
    • A PC VI can be developed to interact with the simulated FPGA model as a more sophisticated way to exercise the FPGA VI inputs and to observe the resulting outputs
  4. Compile the FPGA VI to a bitfile using your own computer or a cloud-based compiler; compiling in the cloud may take a little longer, but it removes the burden from your own machine and permits multiple FPGA VIs to be compiled at once

For more information

  1. FPGA Fundamentals (http://www.ni.com/white-paper/6983/en)
    General introduction to field-programmable gate arrays (FPGAs) and their role in the NI RIO technology platform
  2. NI LabVIEW High-Performance FPGA Developer's Guide (http://www.ni.com/tutorial/14600/en)
    A thoroughly useful resource, available as a PDF download. Detailed discussion of the single-cycle timed loop (SCTL) and how it differs from the conventional while-loop structure.
  3. NI LabVIEW for CompactRIO Developer's Guide (http://www.ni.com/compactriodevguide/)
    A thoroughly useful resource, available as a PDF download. Includes sample code.