Reuse existing and validated VHDL-based circuit functionality in the FPGA block diagram instead of developing new LabVIEW G code to implement the same functionality.
Use cases
Describe desired FPGA functionality with a hardware description language (HDL) instead of (or in concert with) LabVIEW G code
Leverage existing IP (intellectual property) functionality in the form of tested and validated VHDL code
Features
The “IP Integration” node accepts one or more VHDL files that comprise a self-contained system
VHDL “entity” ports appear as icon terminal inputs and outputs accessible to tother elements in the block diagram
Bus-style ports may be pinned out as fixed-point numerical values or as Boolean arrays
The “IP Integration” node must reside in a single-cycle timed loop (SCTL)
All entity input and output ports must be of type “STD_LOGIC” and “STD_LOGIC_VECTOR”
The “IP Integration” node is not a development environment! Use another tool to develop and debug your VHDL code.
Consider including a clock enable signal in the design to ensure that the simulated behavior accurately reflects the actual behavior when the FPGA VI runs.
LabVIEW block diagram elements
Locate these elements with "Quick Drop" (press Ctrl+Space and start typing the name); click on an icon to see more sample code that uses that element:
Example code
Connect your Academic RIO Device to your PC using USBLAN, Ethernet, or Wi-Fi. NOTE: Not all Academic RIO Devices have Ethernet and Wi-Fi connectivity options.
Download and unpack the
fpga_vhdl.zip (for use with NI myRIO 1900)
or the
NIELVISIII-fpga_vhdl.zip (for use with NI ELVIS III)
archive, and then double-click the ".lvproj" file to open the project. NOTE: This project was written for a NI myRIO 1900 or NI ELVIS III connected by USBLAN at IP address 172.22.11.2.
If you are using a different IP address or another Academic RIO Device (Example: NI myRIO 1950 or NI RIO Control Module) do the following:
If using the NI myRIO 1950 or NI RIO Control Module start with the NI myRIO 1900 Archive.
Different IP address: Right-click on the "NI myRIO 1900" Device, choose "Properties", and then enter the new IP address
Different device:
Right-click on the top of the project hierarchy, select "New Targets and Devices", keep the "Existing target or device" option, and then find and select your particular device
Select all of the components under the "NI myRIO 1900" device: click the first one and then shift+click the last one
Drag the selected components to the new device
Right-click the "NI myRIO 1900" device and select "Remove from project"
Run the “FPGA Main” VI and observe the Academic RIO Device onboard LEDs for the Johnson-counter bit pattern: 0000, 0001, 0011, 0111, 1111, 1110, 1100, 1000, and repeat.
Press the onboard button to reverse the shifting direction.
Open the “johnson_counter.vhd” file to review the Johnson counter VHDL implementation.
One single-cycle timed loop (SCTL) contains all logic and I/O (onboard button and LEDs); conditional terminal wired to “False” constant as is typical for FPGA VIs
Johnson counter and NOT gate imported from VHDL code
Binary counter from Xilinx IP library generates clock enable pulse
Locate the subpalettes
IP Integration node
Xilinx IP
Configure the IP integration node for combinational logic
Review VHDL file “not_gate.vhd”
Add VHDL file
Confirm “Entity” and “Architecture” selected properly
Generate the simulation model
Select “No Clock” as the clock signal name (because combinational logic)
Do not select a synchronous reset signal (again because combinational)
Confirm I/O ports are assigned correctly
Configure the IP integration node for sequential logic
Review VHDL file “johnson_counter.vhd”
Add VHDL file
Confirm “Entity” and “Architecture” selected properly
Generate the simulation model
Confirm correct clock signal has been selected
Select the clock enable signal as the “IP Enable Signal”
Configure “RESET” as active-high asynchronous reset signal
Confirm I/O ports are assigned correctly; choose “Q” output as unsigned
Configure the Xilinx IP binary counter
Select output width = 24 and increment value = 1; counter turns over every 2^24 cycles to generate an enable pulse at 40 MHz / 2^24 = 2.38 Hz
Compare resource estimates for “Fabric” or “DSP48” implementation
Select Count Mode = UP
Enable synchronous threshold output with threshold value = 1
Ignore clock enable and reset signals for this basic counter