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FPGA code example

"IP Integration" node for VHDL code reuse

Reuse existing and validated VHDL-based circuit functionality in the FPGA block diagram instead of developing new LabVIEW G code to implement the same functionality.

LabVIEW FPGA block diagram snippet: VHDL code for a 4-bit Johnson counter inserted into an IP Integration node

Use cases


Keep in mind

LabVIEW block diagram elements

Locate these elements with "Quick Drop" (press Ctrl+Space and start typing the name); click on an icon to see more sample code that uses that element:

IP Integration node
Binary Counter
Single-Cycle Timed Loop

Example code

Expected results

https://youtu.be/XagadchTguI (0:46)

Developer walk-through

https://youtu.be/OVZe_BwT7Z8 (6:09)