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RIO Developer Essentials Guide for Academia

"FPGA" target

PC and RIO block diagram with FPGA target highlighted

Develop an FPGA VI
FPGA guide

Develop your own FPGA-targeted VI to take advantage of the unique capabilities of the FPGA target such as high-speed I/O, precision I/O timing, parallel processing, and functionality not offered by the RT processor and Academic RIO Device Toolkit default personality; you can also augment the default personality with your needed capability.

Screenshot of LabVIEW VI block diagram and front panel of 'FPGA Main'

Make your first FPGA application
FPGA procedure

Follow along with this step-by-step tutorial to make a "hello, world!"-like application to experience the advantages of multiple linked VIs running simultaneously on the FPGA target, real-time (RT) target, and desktop computer: (1) "FPGA Main" VI blinks the onboard LEDs and reads the onboard button; these onboard devices physically connect to the FPGA I/O pins, (2) "FPGA testbench" VI runs on the desktop computer for interactive development and debugging of "FPGA Main" in simulation mode prior to compiling to a bitstream file, (3) "RT Main" VI runs as the RT target start-up VI; it runs "FPGA Main", interacts with its front-panel controls/indicators, and communicates with an external desktop computer via network-published shared variables, and (4) "PC Main" VI runs on the desktop computer as a user-friendly human-machine interface (HMI) for remote command and control of "FPGA Main" through the network.

Screenshot of LabVIEW Project Explorer window for newly-created FPGA project

Create a new FPGA project
FPGA procedure

Set up a LabVIEW project for a fully custom FPGA VI.

Screenshots of 'Desktop Execution' node and resulting simulated waveforms

FPGA programming: Simulation techniques
FPGA guide PC guide

Run the VI with simulated I/O or create a testbench on the PC host to apply a test sequence as the FPGA VI input and monitor the resulting output sequence.

Screenshot of sampling probes waveform display

Simulate an FPGA VI
FPGA procedure

Debug your FPGA VI before compiling to a bitfile using execution highlighting, breakpoints, probes, and sampling probes.

LabVIEW PC block diagram snippet: PC reads and writes FPGA I/O nodes in simulation mode

"Desktop Execution" node as an FPGA VI testbench
FPGA code PC code

The PC VI interacts with the FPGA VI in simulation mode to apply a test sequence as the FPGA VI input and monitor the resulting output sequence.

LabVIEW FPGA compiler in the "synthesis" phase

Compile an FPGA VI
FPGA procedure

Compile your FPGA VI to a bitfile using your own computer or a cloud-based compiler.

LabVIEW FPGA block diagram snippet: Timed loop with 10-MHz derived clock domain highlighted

Derived clock domains
FPGA code

Use a derived clock domain to effectively speed up or slow down the FPGA's 40-MHz clock for a selected portion of the FPGA block diagram.

Screenshot of Xilinx IP subpalette and IP Integration node

FPGA programming: IP blocks
FPGA guide

Reuse (import) VHDL code and configure Xilinx IP blocks as drop-in components on the LabVIEW block diagram.

LabVIEW FPGA block diagram snippet: VHDL code for a 4-bit Johnson counter inserted into an IP Integration node

"IP Integration" node for VHDL code reuse
FPGA code

Reuse existing and validated VHDL-based circuit functionality in the FPGA block diagram instead of developing new LabVIEW G code to implement the same functionality.

LabVIEW FPGA block diagram subpalette for Xilinx IP functions

Xilinx IP integration
FPGA code

Configure and use Xilinx IP (intellectual property) modules designed specifically for the Xilinx Zynq FPGA

Screenshot of LabVIEW VI front panel of the default Academic RIO Device FPGA personality

Modify the default Academic RIO Device FPGA personality
FPGA procedure

Add your own functionality to the default Academic RIO Device FPGA "personality" (bitfile) to retain selected Device Express VI capabilities.

LabVIEW FPGA block diagram snippet: Process Loop #1 writes an indicator, Process Loop #2 reads the indicator value with a local variable

Local variable (FPGA)
FPGA code

Use a local variable (front-panel indicator) to communicate between two parallel process loops contained within the same VI.

LabVIEW FPGA block diagrams: VI #1 writes a global variable, VI #2 reads the same global variable

Global variable (FPGA)
FPGA code

Use a global variable to communicate between two parallel process loops contained within different VIs under the same target.

LabVIEW FPGA block diagram snippet: RT VI operates the FPGA front panel

Programmatic front-panel communication with RT
FPGA code RT code

The RT VI operates (writes) the front-panel controls of the FPGA VI and reads its indicators.

LabVIEW RT block diagram snippet: Read an audio frame from FPGA DMA FIFO, process the frame, and write the processed frame back to the FPGA

Stream high-speed data between FPGA and RT with a DMA FIFO
FPGA code RT code

Efficiently transfer blocks of data between the RT and FPGA by direct memory access (DMA) first-in first-out (FIFO) buffers.

LabVIEW RT block diagram snippet: Programmatically set a custom FPGA bitfile; alert the VI to expect myRIO default personality functionality on the custom FPGA bitfile

Augmented default Academic RIO Device FPGA personality and high-precision waveform measurement application example
FPGA code RT code

Load and run a modified version of the default Academic RIO Device personality (FPGA bitfile) augmented by user-defined functionality, for example, to make a high-precision measurement of pulse width.

Diagram showing communication pathways between PC host, RT target, and FPGA target

FPGA/RT and FPGA/host inter-target communication
FPGA guide RT guide PC guide

Transfer data, commands, and status between the FPGA target and a host system (RT or PC).

LabVIEW FPGA block diagram snippet: PC VI operates the FPGA front panel

Programmatic front-panel communication with PC
FPGA code PC code

The PC VI operates (writes) the front-panel controls of the FPGA VI and reads its indicators.

LabVIEW PC block diagram snippet: Read an audio frame from FPGA DMA FIFO, process the frame, and write the processed frame back to the FPGA

Stream high-speed data between FPGA and PC with a DMA FIFO
FPGA code PC code

Efficiently transfer blocks of data between the PC and FPGA by direct memory access (DMA) first-in first-out (FIFO) buffers.