Quickstart Guide
Introduction RIO Academic RIO Application examples Your first RT app Your first FPGA app
Basic procedures System admin File system I/O monitor System controller architecture Timed loops Inter-process communication RT/Host communication RT/FPGA communication FPGA personalities Interrupts Datalogger (file I/O)
Design flow Simulation Inter-process communication RT/host communication Derived clock domain IP blocks FPGA personality
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Glossary How to use About
RIO Developer Essentials Guide for Academia

"MyRIO Toolkit" tag

A high-level overview of the Academic RIO Device architecture and features.
Develop Academic RIO Device applications by writing code exclusively for the RT target, and use Express VIs to access the wide variety of I/O devices implemented by the default Device FPGA personality.
Create a new LabVIEW project for the RT target, use the Academic RIO Device Toolkit and default FPGA personality, and deploy a VI as the start-up application.
Follow along with this step-by-step tutorial to make a "hello, world!"-like application to experience the advantages of multiple linked VIs running simultaneously on the real-time (RT) target and desktop computer: (1) "RT Main" runs as the RT target start-up VI, blinks the onboard LEDs, and reads the onboard button; these onboard devices physically connect to the FPGA I/O pins which are accessed with the Academic RIO Device Toolkit Express VIs and default FPGA personality, and (2) "PC Main" VI runs on the desktop computer as a user-friendly human-machine interface (HMI) for remote command and control of "RT Main" through the network via shared variables hosted on the RT target.
The FPGA "personality" (bitstream configuration file) determines how the RT target interacts with peripheral devices. The personality can also implement custom functionality.

Develop an FPGA VI
FPGA guide

Develop your own FPGA-targeted VI to take advantage of the unique capabilities of the FPGA target such as high-speed I/O, precision I/O timing, parallel processing, and functionality not offered by the RT processor and Academic RIO Device Toolkit default personality; you can also augment the default personality with your needed capability.
Add your own functionality to the default Academic RIO Device FPGA "personality" (bitfile) to retain selected Device Express VI capabilities.
Use an onboard timer or an external event interrupt request (IRQ) to immediately execute a task.
Run a callback VI each time that a digital input transition or an analog input voltage threshold crossing generates an interrupt request (IRQ).
Run a callback VI each time that an FPGA-based interval timer generates an interrupt request (IRQ).
Load and run a modified version of the default Academic RIO Device personality (FPGA bitfile) augmented by user-defined functionality, for example, to make a high-precision measurement of pulse width.