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RIO Developer Essentials Guide for Academia

"MyRIO Toolkit" tag

Diagram of NI myRIO architecture showing RT and FPGA targets, communication subsystems (USBLAN and wireless), file system, I/O, and onboard devices

NI Academic RIO Device architecture overview
RIO guide

A high-level overview of the Academic RIO Device architecture and features.

LabVIEW "myRIO" subpalette showing all available Express VIs

Academic RIO Device Toolkit Express VIs
RT guide

Develop Academic RIO Device applications by writing code exclusively for the RT target, and use Express VIs to access the wide variety of I/O devices implemented by the default Device FPGA personality.

LabVIEW RT icon and ABC blocks

Real-Time (RT) programming: Basic procedures
RT guide

Create a new LabVIEW project for the RT target, use the Academic RIO Device Toolkit and default FPGA personality, and deploy a VI as the start-up application.

Screenshot of LabVIEW VI block diagram and front panels of 'RT Main' and 'PC Main'

Make your first RT application
RT procedure

Follow along with this step-by-step tutorial to make a "hello, world!"-like application to experience the advantages of multiple linked VIs running simultaneously on the real-time (RT) target and desktop computer: (1) "RT Main" runs as the RT target start-up VI, blinks the onboard LEDs, and reads the onboard button; these onboard devices physically connect to the FPGA I/O pins which are accessed with the Academic RIO Device Toolkit Express VIs and default FPGA personality, and (2) "PC Main" VI runs on the desktop computer as a user-friendly human-machine interface (HMI) for remote command and control of "RT Main" through the network via shared variables hosted on the RT target.

LabVIEW RT icon and FPGA icon

RT programming: FPGA personalities
RT guide

The FPGA "personality" (bitstream configuration file) determines how the RT target interacts with peripheral devices. The personality can also implement custom functionality.

PC and RIO block diagram with FPGA target highlighted

Develop an FPGA VI
FPGA guide

Develop your own FPGA-targeted VI to take advantage of the unique capabilities of the FPGA target such as high-speed I/O, precision I/O timing, parallel processing, and functionality not offered by the RT processor and Academic RIO Device Toolkit default personality; you can also augment the default personality with your needed capability.

Screenshot of LabVIEW VI front panel of the default Academic RIO Device FPGA personality

Modify the default Academic RIO Device FPGA personality
FPGA procedure

Add your own functionality to the default Academic RIO Device FPGA "personality" (bitfile) to retain selected Device Express VI capabilities.

LabVIEW RT icon and exclamation point icon

RT programming: Interrupts
RT guide

Use an onboard timer or an external event interrupt request (IRQ) to immediately execute a task.

LabVIEW RT block diagram snippet: Create a digital input transition IRQ (interrupt request), associate with a callback VI

Externally-triggered action using interrupt request (IRQ)
RT code

Run a callback VI each time that a digital input transition or an analog input voltage threshold crossing generates an interrupt request (IRQ).

LabVIEW RT block diagram snippet: Create a timer IRQ (interrupt request), associate with a callback VI

Timer-driven background process using interrupt request (IRQ)
RT code

Run a callback VI each time that an FPGA-based interval timer generates an interrupt request (IRQ).

LabVIEW RT block diagram snippet: Programmatically set a custom FPGA bitfile; alert the VI to expect myRIO default personality functionality on the custom FPGA bitfile

Augmented default Academic RIO Device FPGA personality and high-precision waveform measurement application example
FPGA code RT code

Load and run a modified version of the default Academic RIO Device personality (FPGA bitfile) augmented by user-defined functionality, for example, to make a high-precision measurement of pulse width.