Quickstart Guide
Introduction RIO Academic RIO Application examples Your first RT app Your first FPGA app
Basic procedures System admin File system I/O monitor System controller architecture Timed loops Inter-process communication RT/Host communication RT/FPGA communication FPGA personalities Interrupts Datalogger (file I/O)
Design flow Simulation Inter-process communication RT/host communication Derived clock domain IP blocks FPGA personality
Get connected Email Web services UDP TCP IP addresses
Site Map
Guides Code examples Procedures Tags LabVIEW block diagram elements Targets Communications All pages
Glossary How to use About
RIO Developer Essentials Guide for Academia

"FPGA-PC" communication

The PC VI interacts with the FPGA VI in simulation mode to apply a test sequence as the FPGA VI input and monitor the resulting output sequence.
Transfer data, commands, and status between the FPGA target and a host system (RT or PC).