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"Message" tag

Diagram showing communication pathways three process loops on the RT target

RT inter-process communication
RT guide

Exchange data between process loops running in parallel on the RT target.

Diagram showing communication pathway between PC host and RT target

RT/host inter-target communication
RT guide PC guide

Transfer data, commands, and status between the RT target and a host system.

LabVIEW RT block diagram snippet: PC writes one element to a network stream channel, RT reads the element from the same channel

Send messages through a network stream channel
RT code PC code

Send command and status messages through a low-latency lossless network-based data communication channel between the RT target and PC host system.

LabVIEW RT block diagram snippet: Read an audio frame from FPGA DMA FIFO, process the frame, and write the processed frame back to the FPGA

Stream high-speed data between FPGA and RT with a DMA FIFO
FPGA code RT code

Efficiently transfer blocks of data between the RT and FPGA by direct memory access (DMA) first-in first-out (FIFO) buffers.

Diagram showing communication pathways between PC host, RT target, and FPGA target

FPGA/RT and FPGA/host inter-target communication
FPGA guide RT guide PC guide

Transfer data, commands, and status between the FPGA target and a host system (RT or PC).

LabVIEW PC block diagram snippet: Read an audio frame from FPGA DMA FIFO, process the frame, and write the processed frame back to the FPGA

Stream high-speed data between FPGA and PC with a DMA FIFO
FPGA code PC code

Efficiently transfer blocks of data between the PC and FPGA by direct memory access (DMA) first-in first-out (FIFO) buffers.