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"Inter-target" communication

LabVIEW PC block diagram snippet: PC reads and writes FPGA I/O nodes in simulation mode

"Desktop Execution" node as an FPGA VI testbench
FPGA code PC code

The PC VI interacts with the FPGA VI in simulation mode to apply a test sequence as the FPGA VI input and monitor the resulting output sequence.

LabVIEW PC block diagram snippet: Get PC system time and adjust RT system time to match

Set RT system time/date from PC
RT code PC code

Use the "Set Time" function to adjust the RT system time to match the (assumed accurate) PC system time. Restart the RT target to save the current RT time to be reloaded on each reboot of the Academic RIO Device.

Diagram showing communication pathway between PC host and RT target

RT/host inter-target communication
RT guide PC guide

Transfer data, commands, and status between the RT target and a host system.

LabVIEW FPGA block diagram snippet: RT VI operates the FPGA front panel

Programmatic front-panel communication with RT
FPGA code RT code

The RT VI operates (writes) the front-panel controls of the FPGA VI and reads its indicators.

Shared variables icons in LabVIEW project

Create a network-published shared variable (NPSV)
RT procedure PC procedure

The network-published shared variable (NPSV) behaves like a global variable to link targets through the network.

Front-panel indicator LED with green bound variable indicator

Bind a PC VI front-panel indicator to a network-published shared variable (NPSV)
RT procedure PC procedure

A quick and easy way for a PC HMI (human-machine interface) VI to observe the state of an RT-hosted network-published shared variable (NPSV) without creating any block diagram code; an alternative to programmatically accessing the NPSV value.

LabVIEW RT block diagram snippet: RT and PC read and write the same network-published shared variables

Network-published shared variable (NPSV)
RT code PC code

A network-published shared variable (NPSV) behaves like a global variable that links process loops residing in two or more network-connected targets.

LabVIEW RT block diagram snippet: RT opens a handle to a network-published shared variable and reads its value

Programmatically access a network-published shared variable (NPSV)
RT code PC code

Use the NPSV programmatic API (application programmer's interface) VIs as an alternative method to a shared variable node.

LabVIEW RT block diagram snippet: PC writes one element to a network stream channel, RT reads the element from the same channel

Send messages through a network stream channel
RT code PC code

Send command and status messages through a low-latency lossless network-based data communication channel between the RT target and PC host system.

LabVIEW RT block diagram snippet: RT writes blocks of data to a network stream channel, PC reads the blocks from the same channel

Stream high-speed data through a network stream channel
RT code PC code

Efficiently transfer blocks of data between the RT and PC by network streams.

LabVIEW RT block diagram snippet: Read an audio frame from FPGA DMA FIFO, process the frame, and write the processed frame back to the FPGA

Stream high-speed data between FPGA and RT with a DMA FIFO
FPGA code RT code

Efficiently transfer blocks of data between the RT and FPGA by direct memory access (DMA) first-in first-out (FIFO) buffers.

LabVIEW RT block diagram snippet: Programmatically set a custom FPGA bitfile; alert the VI to expect myRIO default personality functionality on the custom FPGA bitfile

Augmented default Academic RIO Device FPGA personality and high-precision waveform measurement application example
FPGA code RT code

Load and run a modified version of the default Academic RIO Device personality (FPGA bitfile) augmented by user-defined functionality, for example, to make a high-precision measurement of pulse width.

Diagram showing communication pathways between PC host, RT target, and FPGA target

FPGA/RT and FPGA/host inter-target communication
FPGA guide RT guide PC guide

Transfer data, commands, and status between the FPGA target and a host system (RT or PC).

LabVIEW FPGA block diagram snippet: PC VI operates the FPGA front panel

Programmatic front-panel communication with PC
FPGA code PC code

The PC VI operates (writes) the front-panel controls of the FPGA VI and reads its indicators.

LabVIEW PC block diagram snippet: Read an audio frame from FPGA DMA FIFO, process the frame, and write the processed frame back to the FPGA

Stream high-speed data between FPGA and PC with a DMA FIFO
FPGA code PC code

Efficiently transfer blocks of data between the PC and FPGA by direct memory access (DMA) first-in first-out (FIFO) buffers.

LabVIEW front panels of the "Home Security System" application: RT target with virtual user interface and PC host remote interface

System controller application example: Home Security System
RT code PC code

Example of a complete RT system controller based on the Queued Message Handler (QMH) design pattern with multiple parallel task loops implementing behaviors with queued state machines (QSMs), various inter-process communication techniques (queues and local variables), and inter-target communication techniques (network-published shared variables (NPSVs) and network streams). The PC host human-machine interface (HMI) can remotely connect to the system through the network, monitor the status of the security system, and control it remotely.